RE: [sv-bc] SVDB 1619 Examples

I agree that the syntax is similar.

However, one is synthesizable and the other is not.

I agree that it is a problem that tools only give a warning and then
continue. However, I think the reason is that sometimes design files
contain additional code which is not intended to be synthesized, yet
also not surrounded by translate_off.

Your position is clear. Let's leave it at that.

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Clifford E. Cummings
> Sent: Monday, October 15, 2007 2:42 PM
> To: sv-bc@server.eda.org
> Subject: RE: [sv-bc] SVDB 1619 Examples
> 
> Hi, Shalom -
> 
> It was the closest similar syntax that I could test. If 
> Synopsys says they will support the feature in synthesis, I 
> will vote yes, else I will vote no.
> 
> Regards - Cliff
> 
> At 05:36 AM 10/15/2007, Bresticker, Shalom wrote:
> >Cliff,
> >
> >It is still not a similar situation.
> >
> >A variable declaration assignment is a one-time assignment 
> of a value 
> >to a signal. Whether it occurs exactly as an initial block 
> or precedes 
> >the initial block is irrelevant. It is an operation which 
> does not have 
> >a physical equivalent in normal digital circuitry. At the 
> very least, 
> >you need a reset signal to be activated.
> >
> >The default is something entirely different. It models a 
> fixed physical 
> >connection to VCC or VDD. It is fixed as elaboration time. 
> It is really 
> >no different than determining a parameter value depending on whether 
> >the parameter has an override or not.
> >
> >Regards,
> >Shalom
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com Expert 
> Verilog, SystemVerilog, Synthesis and Verification Training
> 
> 
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