[sv-bc] SVDB 1464 - Clif now votes yes.

Hi, All -

I have seen Shalom's update to SVdb-1464 and I now vote yes on the 
updated proposal.

Regards - Cliff

At 04:59 AM 10/14/2007, Bresticker, Shalom wrote:
>Cliff wrote on Mantis 1464:
>
>SVDB 1464 No
>
>As long as we are making corrections to the example, the "assumed to be
>instantiated"
>module is also wrong because the matching internal bus declarations are
>also required.
>
>I would vote yes if the proposed change is modified as follows:
>
>TO
>
>The following example demonstrates the usage of extern module
>declarations.
>
>extern module m (a,b,c,d);
>extern module a #(parameter size= 8, parameter type TP = logic [7:0])
>(input [size:0] a, output TP b);
>
>module top ();
>wire [8:0] a;
>logic [7:0] b;
>wire c, d;
>m mm (.*);
>a aa (.*);
>endmodule
>
>Modules m and a are then assumed to be instantiated as follows:
>
>module top ();
>wire [8:0] a;
>logic [7:0] b;
>m mm (a,b,c,d);
>a aa (a,b);
>endmodule
>
>
>[SB] I agree and will make that change.
>
>Shalom

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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