Re: [sv-bc] confusion in determining the type of an self determined binary expression during evalution of type operator

Gordon Vreugdenhil wrote:
>  For example given packed
> unsigned bit vectors "a" and "b", the LRM does not say anything
> about the precise type of "a[4:5] + b[3:2]".

Are there any dissenters from the idea that this is a packed
bit or logic vector unsigned [1:0]?



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