Re: [sv-bc] confusion in determining the type of an self determined binary expression during evalution of type operator

Greg Jaxon wrote:
> Gordon Vreugdenhil wrote:
>>  For example given packed
>> unsigned bit vectors "a" and "b", the LRM does not say anything
>> about the precise type of "a[4:5] + b[3:2]".
> 
> Are there any dissenters from the idea that this is a packed
> bit or logic vector unsigned [1:0]?

I don't know.  Is this still true for just "a[4:5]"?  In effect,
do you *always* normalize?  Only for selects and non-simple
expressions?

I don't have any basic objection to normalization as long as the
rules for when normalization applies are stated clearly.  I
suspect that normalization will result in a simpler set of rules
and will be closer to Verilog philosophy, but there are questions
in various spaces that would need to be covered.

Gord.
-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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