Feldman, Yulik wrote: > I didn't imply that it has a self-determined type. I just gave examples > of expression kinds that may have a complex data type, self-determined > or context-determined. Yulik, I believe that you are suggesting that a (part)select should not necessarily be normalized but should carry its range information around (more like VHDL). I would almost certainly object to that approach as a general requirement. The reason for the objection is that there is no Verilog precedent for needing that information in general and adding such a requirement would definitely have an impact on simulation performance. Given the limited contexts in which the information is used, it would be better to assume normalization everywhere other than a very few specific circumstances. I know that various people have talked about wanting to have selects on general expressions and that this position impacts that. If someone wants to try to write up a full description of normalization rules and/or un-normalized cases, I'd certainly review it, but I'm likely going to be wary of any deep requirement regarding non-normalized expressions. Gord. -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Oct 16 07:13:48 2007
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