RE: [sv-ac] Re: [sv-bc] 2005: Deferred assertions (new proposal at http://www.verilog.org/mantis/view.php?id=2005)

I agree with Dmitry.

The difference is unambiguous and easy to discern by

the presence or absence of the "property" keyword.

 

Regards,

Doug

 

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Korchemny, Dmitry
Sent: Monday, October 29, 2007 9:18 AM
To: Adam Krolnik; Seligman, Erik
Cc: sv-ac@server.eda.org; sv-bc@server.eda-stds.org
Subject: RE: [sv-ac] Re: [sv-bc] 2005: Deferred assertions (new proposal
at http://www.verilog.org/mantis/view.php?id=2005)

 

But you have different keywords:  "assert" and "assert property".

 

Regards,

Dmitry

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Adam Krolnik
Sent: Monday, October 29, 2007 5:56 PM
To: Seligman, Erik
Cc: sv-ac@server.eda.org; sv-bc@server.eda-stds.org
Subject: [sv-ac] Re: [sv-bc] 2005: Deferred assertions (new proposal at
http://www.verilog.org/mantis/view.php?id=2005)

 


Hello all;

My concern with this new syntax is that you are now very close to
concurrent assertions.

Deferred:
assert  (#0 | event_expr) ...

Concurrent
assert property ...

If you keep the ability for an event expression, then you have two
seemingly same syntax constructions.
This may cause confusion to users. 

SV-AC what do you think about this confusion between deferred and
concurrent forms ? 



-- 
    Soli Deo Gloria
    Adam Krolnik
    Director of Design Verification
    VeriSilicon Inc.
    Plano TX. 75074
    Co-author "Assertion-Based Design", "Creating Assertion-Based IP"
 
 
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