RE: [sv-ac] Re: [sv-bc] 2005: Deferred assertions (new proposal at http://www.verilog.org/mantis/view.php?id=2005)

From: Lisa Piper <piper_at_.....>
Date: Mon Oct 29 2007 - 10:17:23 PDT
I agree with Erik - I don't think it is any more confusing than
immediates versus concurrents.

 

Lisa

 

________________________________

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Seligman, Erik
Sent: Monday, October 29, 2007 12:31 PM
To: Adam Krolnik
Cc: sv-ac@eda.org; sv-bc@eda-stds.org
Subject: RE: [sv-ac] Re: [sv-bc] 2005: Deferred assertions (new proposal
at http://www.verilog.org/mantis/view.php?id=2005)

 

Hmmm... Someone else made a similar point in private email.

 

But isn't this already a problem in current SVA?  For example, the
following two are both legal in some contexts:

    assert (foo);

    assert property (foo);

 

I'm not sure I see how (#0 | event expr) vs. 'defer' makes a major
difference in this confusion-- the root cause is the similarity between
immediate & concurrent asserts in the language.  

 

Are other people concerned about this?  Are there suggestions for
providing this functionality but making it less confusing?

 

 

________________________________

From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Adam Krolnik
Sent: Monday, October 29, 2007 8:56 AM
To: Seligman, Erik
Cc: sv-ac@server.eda.org; sv-bc@server.eda-stds.org
Subject: [sv-ac] Re: [sv-bc] 2005: Deferred assertions (new proposal at
http://www.verilog.org/mantis/view.php?id=2005)


Hello all;

My concern with this new syntax is that you are now very close to
concurrent assertions.

Deferred:
assert  (#0 | event_expr) ...

Concurrent
assert property ...

If you keep the ability for an event expression, then you have two
seemingly same syntax constructions.
This may cause confusion to users. 

SV-AC what do you think about this confusion between deferred and
concurrent forms ? 




-- 
    Soli Deo Gloria
    Adam Krolnik
    Director of Design Verification
    VeriSilicon Inc.
    Plano TX. 75074
    Co-author "Assertion-Based Design", "Creating Assertion-Based IP"
 
 


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Received on Mon Oct 29 10:18:09 2007

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