> > Maybe someone in SV-BC can clarify. The question is, given > > the declarations below is the initial value of w 1'bz or 1'bx? > > > > reg r; > > wire w; > > assign w = r; [the initial value of w] > Should be 1'bx. > Since r is unitialized, it is 1'bx. > w is driven by r. 1'bx even in the Preponed region of the very first timeslot??? Surely the first activation of the continuous assignment cannot occur until the Active region of time 0? Or is this too mechanistic a view of continuous assignment? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Nov 19 10:00:45 2007
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