RE: [sv-bc] RE: [sv-ac] sampled assertion function vs data types - refereing to prior simulation

Ah, if you mean that, then yes, it is 1'bz till the assign affects it,
which is after simulation starts.

Shalom 

> -----Original Message-----
> From: Jonathan Bromley [mailto:jonathan.bromley@doulos.com] 
> Sent: Monday, November 19, 2007 8:00 PM
> To: Bresticker, Shalom; john.havlicek@freescale.com; Korchemny, Dmitry
> Cc: danielm@aldec.com.pl; sv-ac@server.eda-stds.org; 
> sv-bc@server.eda.org
> Subject: RE: [sv-bc] RE: [sv-ac] sampled assertion function 
> vs data types - refereing to prior simulation
> 
> > > Maybe someone in SV-BC can clarify.  The question is, given the 
> > > declarations below is the initial value of w 1'bz or 1'bx?
> > > 
> > >   reg r;
> > >   wire w;
> > >   assign w = r;
> 
> [the initial value of w]
> > Should be 1'bx.
> > Since r is unitialized, it is 1'bx.
> > w is driven by r.
> 
> 1'bx even in the Preponed region of the very first timeslot???
> Surely the first activation of the continuous assignment 
> cannot occur until the Active region of time 0?
> Or is this too mechanistic a view of continuous assignment?
> --
> Jonathan Bromley, Consultant
> 
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