Hi Folks: I believe what you say about the initial value of w being 1'bz. But what does the sentence Nets with drivers shall assume the output value of their drivers. in the middle of the paragraph The default initialization value for a net shall be the value z. Nets with drivers shall assume the output value of their drivers. The trireg net is an exception. The trireg net shall default to the value x, with the strength specified in the net declaration (small, medium, or large). mean? Your interpretation is that this sentence is not talking about initial values before the first timestep, so I find it confusing for this sentence to appear in this place. J.H. > X-ExtLoop1: 1 > X-IronPort-AV: E=Sophos;i="4.21,437,1188802800"; > d="scan'208";a="210724217" > X-MimeOLE: Produced By Microsoft Exchange V6.5 > Content-class: urn:content-classes:message > Date: Mon, 19 Nov 2007 20:03:03 +0200 > X-MS-Has-Attach: > X-MS-TNEF-Correlator: > Thread-Topic: [sv-bc] RE: [sv-ac] sampled assertion function vs data types - refereing to prior simulation > Thread-Index: Acgq1Mqz7xGwUnomSdWG2g4cRNtQOQAAD9vgAAAmwaAAACtN0A== > From: "Bresticker, Shalom" <shalom.bresticker@intel.com> > Cc: <danielm@aldec.com.pl>, <sv-ac@eda-stds.org>, <sv-bc@eda.org> > X-OriginalArrivalTime: 19 Nov 2007 18:03:03.0889 (UTC) FILETIME=[6E1E0C10:01C82AD6] > > Ah, if you mean that, then yes, it is 1'bz till the assign affects it, > which is after simulation starts. > > Shalom=20 > > > -----Original Message----- > > From: Jonathan Bromley [mailto:jonathan.bromley@doulos.com]=20 > > Sent: Monday, November 19, 2007 8:00 PM > > To: Bresticker, Shalom; john.havlicek@freescale.com; Korchemny, Dmitry > > Cc: danielm@aldec.com.pl; sv-ac@server.eda-stds.org;=20 > > sv-bc@server.eda.org > > Subject: RE: [sv-bc] RE: [sv-ac] sampled assertion function=20 > > vs data types - refereing to prior simulation > >=20 > > > > Maybe someone in SV-BC can clarify. The question is, given the=20 > > > > declarations below is the initial value of w 1'bz or 1'bx? > > > >=20 > > > > reg r; > > > > wire w; > > > > assign w =3D r; > >=20 > > [the initial value of w] > > > Should be 1'bx. > > > Since r is unitialized, it is 1'bx. > > > w is driven by r. > >=20 > > 1'bx even in the Preponed region of the very first timeslot??? > > Surely the first activation of the continuous assignment=20 > > cannot occur until the Active region of time 0? > > Or is this too mechanistic a view of continuous assignment? > > -- > > Jonathan Bromley, Consultant > >=20 > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > >=20 > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,=20 > > Hampshire, BH24 1AW, UK > > Tel: +44 (0)1425 471223 Email:=20 > > jonathan.bromley@doulos.com > > Fax: +44 (0)1425 471573 Web:=20 > > http://www.doulos.com > >=20 > > The contents of this message may contain personal views which=20 > > are not the views of Doulos Ltd., unless specifically stated. > >=20 > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Nov 20 06:22:34 2007
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