Steven, many thanks for the helpful clarification. > A simulated wire will start with whatever value the simulator > initializes it to before the simulation starts. Understood. > I can tell you that NC-Verilog [...] > starts all nets at x and transitions them to z at time > zero if not driven. This x->z transition creates an event [...] > So the answer in NC-Verilog will be x. But I don't > think you can count on that being the answer in other > implementations. That's all very reasonable. But there remains the problem that assertions need to inspect the values of things in Preponed of time 0, when using $past() and its friends. I don't want to prejudge what AC thinks, but I'm guessing that either 'x or 'z would be acceptable to them - but it needs to be specified. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Nov 21 01:41:09 2007
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