Re: [sv-bc] RE: [sv-ac] sampled assertion function vs data types - refereing to prior simulation

Hi Folks:

If the clocking event of an assertion occurs in the first timestep,
then that assertion will be evaluated in the first timestep and the
first timestep Preponed values of the expressions will be used for the
part of the assertion evaluation that is performed in the first
timestep.

This does not require the use of $past or other sampled value function
in the assertion.

The use of $past or other sampled value function may result in a
dependency of an assertion expression evaluation in a later timestep
on the Preponed values in the first timestep.

My opinion is that SV-BC should be defining what the first timestep
Preponed values are.  I thought that those were well defined, but
perhaps that is not the case.

If for certain kinds of nets, variables, etc., there is no well
defined Preponed value in the first timestep, then the evaluation of
an assertion that relies on such a value will not be well defined.

J.H.


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> Steven,
> 
> many thanks for the helpful clarification.
> 
> > A simulated wire will start with whatever value the simulator 
> > initializes it to before the simulation starts. 
> 
> Understood.
> 
> > I can tell you that NC-Verilog [...]
> > starts all nets at x and transitions them to z at time
> > zero if not driven.  This x->z transition creates an event
> [...]
> > So the answer in NC-Verilog will be x.  But I don't
> > think you can count on that being the answer in other
> > implementations.
> 
> That's all very reasonable.  But there remains the problem
> that assertions need to inspect the values of things in 
> Preponed of time 0, when using $past() and its friends.
> I don't want to prejudge what AC thinks, but I'm guessing
> that either 'x or 'z would be acceptable to them - but 
> it needs to be specified.
> -- 
> Jonathan Bromley, Consultant
> 
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