[sv-bc] RE: [sv-ec] Is interface ref variable automatic?

ref *ports* are discussed in 19.12.1 of 1800-2005 LRM.

Note that inout *arguments* for tasks/functions and inout *ports* for
modules/interfaces/programs also have different semantics and are
discussed in the same relevant sections.

> -----Original Message-----
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org]
On
> Behalf Of Surya Pratik Saha
> Sent: Wednesday, December 12, 2007 8:40 PM
> To: Mark Hartoog
> Cc: sv-bc@server.eda.org; sv-ec@server.eda.org; Adhip Das
> Subject: Re: [sv-ec] Is interface ref variable automatic?
> 
> Hi Mark,
> I am not fully satisfied with your response. Because in SV 1800 LRM,
> 'ref' arguments are discussed only in Task-Function section, no where
> else. But module/interface/program can also have 'ref' arguments. So
we
> can not conclude the behaviour mentioned in LRM is only for
Task-function.
> 
> LRM should be clear on that. What do you think. I don't want to make
any
> assumption.
> 
> Regards
> Surya
> 
> 
> 
> -------- Original Message  --------
> Subject: Re:[sv-ec] Is interface ref variable automatic?
> From: Mark Hartoog <Mark.Hartoog@synopsys.com>
> To: Surya Pratik Saha <spsaha@cal.interrasystems.com>, sv-bc@eda.org,
> sv-ec@eda.org
> Cc: "Adhip Das" <adhip@cal.interrasystems.com>
> Date: Thursday, December 13, 2007 1:30:10 AM
> > This example is legal. Section 12.4.2 is talking about ref arguments
> > to tasks and functions. In your example you have a ref port on an
> > interface. You cannot attach a automatic variable to a ref port of
> > a module, interface or program, so no such restriction exists for
> > ref ports.
> >
> >
> >> -----Original Message-----
> >> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On
> >> Behalf Of Surya Pratik Saha
> >> Sent: Wednesday, December 12, 2007 12:43 AM
> >> To: sv-bc@eda.org; sv-ec@eda.org
> >> Cc: Adhip Das
> >> Subject: [sv-ec] Is interface ref variable automatic?
> >>
> >> Hi,
> >>
> >> Consider the following testcase,
> >>
> >> interface intf (ref bit [3:0] ba);
> >> endinterface
> >>
> >> module named1 ();
> >>    bit [3:0] ba;
> >>    assign o1 =  i2.ba;
> >>    intf i2 (ba);
> >> endmodule
> >>
> >> As per systemverilog LRM 1800-2005, section 12.4.2 Pass by
reference:
> >>
> >> "Because a variable passed by reference may be an automatic
> >> variable, a ref argument shall not be used in any context
> >> forbidden for automatic variables."
> >>
> >> Could you please tell me whether the above testcase is
> >> erroneous or not?
> >> I guess, it is erroneous because ref variable(which should be
> >> treated as automatic variable) is hierarchically referred(i2.ba).
> >>
> >> --
> >> Regards
> >> Surya
> >>
> >>
> >>
> >>
> >>
> >> --
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> >
> >
> >
> >
> >
> >
> 
> 
> 
> 
> 
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