[sv-bc] Is interface ref variable automatic?

Hi,

Consider the following testcase,

interface intf (ref bit [3:0] ba);
endinterface

module named1 ();
   bit [3:0] ba;
   assign o1 =  i2.ba;
   intf i2 (ba);
endmodule

As per systemverilog LRM 1800-2005, section 12.4.2 Pass by reference:

"Because a variable passed by reference may be an automatic variable, a ref
argument shall not be used in any context forbidden for automatic 
variables."

Could you please tell me whether the above testcase is erroneous or not?
I guess, it is erroneous because ref variable(which should be treated as
automatic variable) is hierarchically referred(i2.ba).

-- 
Regards
Surya






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