RE: [sv-bc] Is interface ref variable automatic?

Again, you are confusing the rules for ref *arguments* with ref *ports*.

And as Brad noted in an earlier, a port could never refer to an
automatic because you can't declare an automatic in the same scope as
you can a module/interface instance, nor could you reference an
automatic from outside the scope it was declared.

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Surya Pratik Saha
> Sent: Wednesday, December 12, 2007 5:55 AM
> To: sv-ec@server.eda-stds.org; sv-bc@server.eda-stds.org
> Cc: Adhip Das
> Subject: [sv-bc] Is interface ref variable automatic?
> 
> Hi,
> 
> Consider the following testcase,
> 
> interface intf (ref bit [3:0] ba);
> endinterface
> 
> module named1 ();
>    bit [3:0] ba;
>    assign o1 =  i2.ba;
>    intf i2 (ba);
> endmodule
> 
> As per systemverilog LRM 1800-2005, section 12.4.2 Pass by reference:
> 
> "Because a variable passed by reference may be an automatic variable,
a
> ref
> argument shall not be used in any context forbidden for automatic
> variables."
> 
> Could you please tell me whether the above testcase is erroneous or
not?
> I guess, it is erroneous because ref variable(which should be treated
as
> automatic variable) is hierarchically referred(i2.ba).
> 
> --
> Regards
> Surya
> 
> 
> 
> 
> 
> 
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