RE: [sv-bc] Mantis 1984

So what do people do with

module test(input int i, output o);
bit o;
endmodule


This is related to what was asked in
http://www.eda-stds.org/sv-bc/hm/7784.html for t/f.

Dave

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Steven Sharp
> Sent: Monday, December 17, 2007 7:47 AM
> To: sv-bc@server.eda-stds.org; Brad.Pierce@synopsys.com
> Subject: RE: [sv-bc] Mantis 1984
> 
> 
> >From: "Brad Pierce" <Brad.Pierce@synopsys.com>
> 
> >Are you saying that port declarations like
> >
> >   module test(input int i, output o);
> >   endmodule
> >
> >were illegal in IEEE Std 1800-2005?
> 
> Yes.  This was discussed when the text was approved, because of
> concerns with backward compatibility with the previous Accellera LRM.
> 
> 
> >Do any existing tools really error on this?
> 
> We allow it, with at most a warning, because of the potential backward
> compatibility issue.  I think we may treat it as a 2-state net, with
> semantics of our own devising, rather than as a variable.
> 
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
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