If we want to encourage logic use, then, why 'wire scalered reg' is
allowed. I think either, reg should be totally disallowed as net data
type, or should be allowed for all. Because current restriction is
somehow confusing.
Regards
Surya
-------- Original Message --------
Subject: Re:[sv-ec] 'reg' after net type
From: Rich, Dave
<Dave_Rich@mentor.com>
To: Surya Pratik Saha
<spsaha@cal.interrasystems.com>,
sv-ec@eda.org,
sv-bc@eda.org
Date: Tuesday, December 18, 2007 3:07:51 PM
The reason
for the restriction was to
prevent typographical errors that would be very difficult to detect the
difference between
tri reg
and
trireg
It also is
to encourage people to use logic
instead of reg as a
data type because wire
reg is visually contradictory to anyone familiar with
Verilog.
Dave
Hi,
As per SV LRM (6.6 Net declarations draft 4), following text is
mentioned:
A lexical restriction applies to
the use of
the reg keyword in a net or port declaration. A net type keyword shall
not be
followed directly by the reg keyword. Thus, the following declarations
are in
error:
Is there special meaning for that restriction. If 'wire
scalared
reg' is allowed why then 'wire reg' is not allowed. Some tools pass
'wire reg
r' syntax.
--
Regards
Surya
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Received on Tue Dec 18 01:52:24 2007