RE: [sv-bc] Mantis 1984

When design teams move more fully in to SV and also couple an SV
Testbench, you should.  I've (general user) had this issue come up
already.  We worked around it by changing the declaration in the RTL to
accommodate the restriction.  The issues arose for us when we had one
command ASIC testbench and utilized Module Stubbing to get our Island
Testbenches.  This necessitated the TB to drive some signals the are
also driven (via initial statements) in our RTL.  As a result we had to
ensure all Ports were of type wire and not var and thus not 2-state.

My 2cents

Regards,
Bryan

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Steven Sharp
Sent: Monday, December 17, 2007 9:53 PM
To: sv-bc@eda-stds.org; Brad.Pierce@synopsys.com
Subject: RE: [sv-bc] Mantis 1984


>From: "Brad Pierce" <Brad.Pierce@synopsys.com>

>Then we should finally address ballot issue 228
> 
>     http://www.eda-stds.org/svdb/view.php?id=694
> 
>Back in 2005 I voted against deferring this issue.

I think it would be good to address this.  However, I have not been
hearing any demand for 2-state nets from users.

I have been hearing requests for real nets, for use in simple analog
modelling.  However, these requests seem to include a desire for
multiple drivers and a variety of driver resolution algorithms.

Steven Sharp
sharp@cadence.com


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