[sv-bc] var on inputs

For var inputs should we allow to have such input driven by both - port
connection, and porcedural block like in below example?
 
 
module top;
        wire w;
        sub uut(w); //< input of sub is driven by port connection
endmodule
 

module sub (input reg i);
        initial i=1;  //input of sub is driven by procedural assignment
        initial #0 $display(i);
endmodule

 
DANiel

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