RE: [sv-bc] Mantis 1828

Jonathan,

If you use always_ff, then in some synthesis tools you will get a
warning, such as

  Warning: ... Netlist for always_ff block contains a latch. ...

module test(input clk, rst, in0, in2, output logic [2:0] q);
always_ff @(posedge clk or posedge rst)
        if (rst)
                q[2:0] <= 0;
        else begin
                q[2] <= in2;
                q[0] <= in0;
        end
endmodule 

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Jonathan Bromley
Sent: Wednesday, February 13, 2008 9:22 AM
To: Bresticker, Shalom; sv-bc@eda.org
Subject: RE: [sv-bc] Mantis 1828

> Another complication on this is a case like the following:
> 
> always @(posedge clk or posedge rst)
> 	if (rst)
> 		q[2:0] <= 0;
> 	else begin
> 		q[2] <= in2;
> 		q[0} <= in0;
> 	end
[...]
> So should always_ff flag an error in such a case?

Since this is my personal second most frequent design mistake (just
behind the opposite one, resetting some but not all of the registers) I
would quite like to see the warning (error?).
I can easily suppress it with a tweak that is completely harmless, and
odd enough to be almost self-documenting:

  always @(posedge clk or posedge rst)
  	if (rst)
  		q[2:0] <= 0;
  	else begin

            q <= q; // suppress warnings about unclocked
                    // registers with a reset

  		q[2] <= in2;
  		q[0} <= in0;
  	end
--
Jonathan Bromley, Consultant

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