Re: [sv-bc] Mantis 1828

Hello all;

When someone else may be reviewing the code, they may not understand the 
line and the comment.
It would simply be more straightforward to include

     q[1] <= 1'b0;

since this explicitly tells all tools what is being expected.  A warning 
would be a nice thing to do, especially since it has an easy way to 
remove the warning.

 

Brad Pierce wrote:
> Jonathan,
>
> If you use always_ff, then in some synthesis tools you will get a
> warning, such as
>
>   Warning: ... Netlist for always_ff block contains a latch. ...
>
> module test(input clk, rst, in0, in2, output logic [2:0] q);
> always_ff @(posedge clk or posedge rst)
>         if (rst)
>                 q[2:0] <= 0;
>         else begin
>                 q[2] <= in2;
>                 q[0] <= in0;
>         end
> endmodule 
>
> -- Brad
>
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
> Jonathan Bromley
> Sent: Wednesday, February 13, 2008 9:22 AM
> To: Bresticker, Shalom; sv-bc@eda.org
> Subject: RE: [sv-bc] Mantis 1828
>
>   
>> Another complication on this is a case like the following:
>>
>> always @(posedge clk or posedge rst)
>> 	if (rst)
>> 		q[2:0] <= 0;
>> 	else begin
>> 		q[2] <= in2;
>> 		q[0} <= in0;
>> 	end
>>     
> [...]
>   
>> So should always_ff flag an error in such a case?
>>     
>
> Since this is my personal second most frequent design mistake (just
> behind the opposite one, resetting some but not all of the registers) I
> would quite like to see the warning (error?).
> I can easily suppress it with a tweak that is completely harmless, and
> odd enough to be almost self-documenting:
>
>   always @(posedge clk or posedge rst)
>   	if (rst)
>   		q[2:0] <= 0;
>   	else begin
>
>             q <= q; // suppress warnings about unclocked
>                     // registers with a reset
>
>   		q[2] <= in2;
>   		q[0} <= in0;
>   	end
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
> 1AW, UK
> Tel: +44 (0)1425 471223                   Email:
> jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573                           Web:
> http://www.doulos.com
>
> The contents of this message may contain personal views which are not
> the views of Doulos Ltd., unless specifically stated.
>
> --
> This message has been scanned for viruses and dangerous content by
> MailScanner, and is believed to be clean.
>
>
>
>   

-- 
    Soli Deo Gloria
    Adam Krolnik
    Director of Design Verification
    VeriSilicon Inc.
    Plano TX. 75074
    Co-author "Assertion-Based Design", "Creating Assertion-Based IP"


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.