> If you use always_ff, then in some synthesis tools you will get a > warning, such as > > Warning: ... Netlist for always_ff block contains a latch. ... > > module test(input clk, rst, in0, in2, output logic [2:0] q); > always_ff @(posedge clk or posedge rst) > if (rst) > q[2:0] <= 0; > else begin > q[2] <= in2; > q[0] <= in0; > end > endmodule Indeed so. But I would also expect to receive such a warning if using a traditional clocked 'always'; the implication of the code for hardware is presumably the same in both cases. The *only* win from always_ff is the fact that it licenses simulators to flag this and other related errors. Oh, I suppose there's the strange posedge...iff... thing. I never really saw the point of that :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Feb 13 13:24:13 2008
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