RE: [sv-bc] Does `\'" violate V95 compatibility?

From: Rich, Dave <Dave_Rich_at_.....>
Date: Wed Mar 05 2008 - 00:07:47 PST
Yes it is relevant. Actually, Greg's first example is not relevant

In Verilog it is legal to

`define \`"  42

You'd invoke this using `\`" , but according to P1800-2008 draft 4:

 

A `\`" indicates that the expansion should include the escape sequence
\".

 

because that last sentence is referring to text in the body of the
macro, not the macro identifier.

 

His modified example IS part of the dilemma described in 1537: you can't
have the functionality defined in the draft LRM AND also have backward
compatibility with 1364-2005.

 

 

 

> -----Original Message-----

> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On

> Behalf Of Bresticker, Shalom

> Sent: Tuesday, March 04, 2008 11:40 PM

> To: Steven Sharp; sv-bc@server.eda.org; Greg.Jaxon@synopsys.com

> Subject: RE: [sv-bc] Does `\'" violate V95 compatibility?

> 

> But is that relevant to Greg's question?

> Compatibility on independent issues is considered independently.

> 

> Shalom

> 

> > -----Original Message-----

> > From: owner-sv-bc@server.eda.org

> > [mailto:owner-sv-bc@server.eda.org] On Behalf Of Steven Sharp

> > Sent: Tuesday, March 04, 2008 11:16 PM

> > To: sv-bc@server.eda.org; Greg.Jaxon@synopsys.com

> > Subject: Re: [sv-bc] Does `\'" violate V95 compatibility?

> >

> > Mantis 1537 describes a case where we can maintain V95

> > compatibility, but that might not be what most people would

> > prefer.  If we maintain that compatibility, there does not

> > seem to be a way to use '' to paste something onto the end of

> > an escaped identifier.

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Received on Wed Mar 5 00:08:53 2008

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