In the example from previous email slice from array of instances is used on port list. Can it be used in other places like ie: module sub; int data; endmodule module top; sub uut[0:9](); initial uut[1:4].data = 1; //???????? legal endmodule DANiel _____ From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce Sent: Tuesday, March 25, 2008 7:52 AM To: sv-ec@server.eda.org; sv-bc@server.eda.org Subject: [sv-bc] RE: [sv-ec] Multidim array of interfaces - supported? Subhamoy, I think it should be legal to slice an MDA of array instances in this way and connect them to a port of the same type and shape, because what isn't prohibited is usually allowed. As you said, "I did not find any LRM section/verse commenting on that." But I didn't find any prohibitions on it either. n Brad From: Subhamoy Pal [mailto:spal@Magma-DA.COM] Sent: Monday, March 24, 2008 11:26 PM To: Brad Pierce; sv-ec@eda.org; sv-bc@eda.org Subject: RE: [sv-ec] Multidim array of interfaces - supported? Thanks Brad for your comment. Now I believe the following case should also be correct where I pass a part-select to the squat_1 instantiation. Isn't it? Test ==== interface ifc; bit clk_in; bit clk_out; logic [7:0] data; endinterface module squat_1(ifc Rx[0:1][0:2]); //2-dim array type endmodule module test; ifc Rx[0:2][0:2](); squat_1 squat_1(Rx[1:2]); //array type is 2-dim endmodule _____ From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Brad Pierce Sent: Tuesday, March 25, 2008 11:29 AM To: sv-ec@eda.org; sv-bc@eda.org Subject: RE: [sv-ec] Multidim array of interfaces - supported? Subhamoy, In my opinion, the LRM allows you to instantiate an MDA of interface instances in the same way as you would an MDA of module instances. For the latter, see the examples in 19.12.5. n Brad From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Subhamoy Pal Sent: Monday, March 24, 2008 10:46 PM To: sv-ec@eda.org; sv-bc@eda.org Subject: [sv-ec] Multidim array of interfaces - supported? Hi, I am little confused over array of interface construct in SV-2005 LRM. It seems most of the standard tools/simulators supports one dimensional array of interface; however they don't support multi-dimensional array of interfaces. Does language prohibits that? I did not find any LRM section/verse commenting on that. Can you suggest me what is per standard? Your suggestion is important to me. Thanks, Subhamoy Example1 - (supported by standard tools/simulators) ======== interface ifc; bit clk_in; bit clk_out; logic [7:0] data; endinterface module squat_1(ifc Rx[0:2]); endmodule module squat_2(ifc Tx); endmodule module test; ifc Rx[0:2](); ifc Tx(); squat_1 squat_1(Rx); squat_2 squat_2(Tx); endmodule Example2 - (standard tools/simulators error out) ======== interface ifc; bit clk_in; bit clk_out; logic [7:0] data; endinterface module squat_1(ifc Rx[0:2][0:2]); endmodule module squat_2(ifc Tx); endmodule module test; ifc Rx[0:2][0:2](); ifc Tx(); squat_1 squat_1(Rx); squat_2 squat_2(Tx); endmodule -- This message has been scanned for viruses and dangerous content by <http://www.mailscanner.info/> MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by <http://www.mailscanner.info/> MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by <http://www.mailscanner.info/> MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Mar 27 06:11:31 2008
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