RE: [sv-bc] E-mail Ballot: Respond by 8am PDT, Tuesday, March 25

From: danielm <danielm_at_.....>
Date: Thu Mar 27 2008 - 06:51:43 PDT
There is one more situation which is not explicitly addressed by yours
proposal and maybe it should.
The problem is what should happened when port kind is net (basing on rules
defined in yours doc) but data type is fobbidden for a wire (ie all 2 val
types and others)

module mh1(int x);              // inout wire int x
module mh5(input int x);                // input wire int x
module mh11(output wire intr x);      // output wire int x

I was asking about this before and as i remmeber it is not defined and
currently tool dependent - maybe this probposal is good place to make this
clear.

There are 3 solutions:
- always forbid such code - syntax error
- if port kind is not given explicitly in such cases change implicitly the
kind into variable. If kind is given explicitly print an error
- allow 2val types to be a net.

Sorry for so late responce - but I've hit the problem once more now.


DANiel

-----Original Message-----
From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Wednesday, March 19, 2008 11:05 AM
To: Warmke, Doug; Maidment, Matthew R; sv-bc@server.eda.org
Subject: RE: [sv-bc] E-mail Ballot: Respond by 8am PDT, Tuesday, March 25

Thanks for the compliment.

I agree about adding signedness.

I changed two examples to the following:

module mh10(output signed [5:0] x); // output wire logic signed [5:0] x

module mh1(integer x, signed [5:0] y);         // inout wire integer x
                                               // inout wire logic signed
[5:0] y

Regards,
Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Warmke, Doug
> Sent: Wednesday, March 19, 2008 11:29 AM
> To: Maidment, Matthew R; sv-bc@server.eda.org
> Subject: RE: [sv-bc] E-mail Ballot: Respond by 8am PDT, Tuesday, March 
> 25
> 
> I vote YES on both.
> 
> Note to Shalom:  Great work on 1465 - much appreciated.
> What would you think about adding one or two more examples that make 
> use of a signedness variation?  That would seem to round out the 
> examples.
> 
> Thanks,
> Doug
> 
> -----Original Message-----
> From: owner-sv-bc@server.eda.org
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Maidment, Matthew R
> Sent: Tuesday, March 18, 2008 11:43 PM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] E-mail Ballot: Respond by 8am PDT, Tuesday, March 25
> 
> 
> -You have until 8am PDT, Tuesday, March 25, 2008 to respond -An issue 
> passes if there are zero NO votes and half of the eligible  voters 
> respond with a YES vote.
> -If you vote NO on any issue, your vote must be accompanied by a 
> reason.
>  The issue will then be up for discussion during a future conference 
> call.
> -Note: For some issues, the proposed action is captured in the bug 
> note
>        (resolve as duplicate, already addressed, etc.). 
> 
> As of the March 17, 2008 meeting, the eligible voters are:
> 
> Brad Pierce        
> Shalom Bresticker  
> Cliff Cummings      
> Mark Hartoog        
> Francoise Martinolle
> Karen Pieper       
> Dave Rich          
> Steven Sharp       
> Gordon Vreugdenhil
> Stu Sutherland
> Alex Gran
> Don Mills
> Heath Chambers
> Tom Alsop
> Doug Warmke
> 
> 
> SVDB 1465 ___Yes   ___No
> http://www.eda.org/svdb/view.php?id=1465
> 
> SVDB 1769 ___Yes   ___No
> http://www.eda.org/svdb/view.php?id=1769
> 
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Received on Thu Mar 27 06:52:39 2008

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