[sv-bc] RE: [sv-ec] Querry regarding Interface

According to http://www.project-veripage.com/interface_1.php

  "An interface can contain initial and always blocks, and hence it is
possible for an interface to have blocks of code that sends stimulii
through its variables."

According to the LRM

  "In addition to task and function methods, an interface can also
contain processes (i.e., initial or always blocks) and continuous
assignments, which are useful for system level modeling and testbench
applications. This allows the interface to include, for example, its own
protocol checker that automatically verifies that all modules connected
via the interface conform to the specified protocol. Other applications,
such as functional coverage recording and reporting, protocol checking,
and assertions can also be built into the interface."

> The main aim of interface as we all know is to encapsulate
communication.

Sutherland gives the following example, which looks like communication
to me

     interface fifo_channel ;
           ...
       // calculate fifo_empty flag
       always_ff @(posedge read_clock, negedge read_resetN) begin
          if (!read_resetN) fifo_empty <= 0;
          else fifo_empty <= (rd_ptr_next == rd_ptr_synced);
      end
      ...
     endinterface

-- Brad

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Surya Pratik Saha
Sent: Wednesday, April 02, 2008 9:56 PM
To: sv-ec@eda.org; sv-bc@eda.org
Cc: Sandeep Jana; 'Pradip Mukhopadhyay'
Subject: [sv-ec] Querry regarding Interface

Hello,
    The main aim of interface as we all know is to encapsulate
communication. If that is the motto then bundling variables and wires in
interfaces and declaring communication protocol should be enough.So what
is the motivation behind supporting always blocks or concurrent
assignment statements inside interface which will basically realize some
logic between the different variables or wires in the interface ? We
could have anyway written the same logic in the module instantiating the
interfaces or another module having that logic and later instantiated
inside the module.
(Please refer to the example below)

interface intf(input bit addsub, input byte data [1:0], output byte q);
function automatic byte add(byte data [1:0]);
return data[0]+data[1];
endfunction
task automatic sub;
q = data[1] - data[0];
endtask
always @*
if (addsub)
q = add(data);
else
sub;
endinterface

module hierRef2(input byte data [1:0], output byte q[1:0]);
intf i1(1'b1, data, q[0]);
endmodule

Regards
Surya








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