[sv-bc] Querry regarding Interface

Hello,
    The main aim of interface as we all know is to encapsulate
communication. If that is the motto then bundling variables and wires in
interfaces and declaring communication protocol should be enough.So what
is the motivation behind supporting always blocks or concurrent
assignment statements inside interface which will basically realize some
logic between the different variables or wires in the interface ? We
could have anyway written the same logic in the module instantiating the
interfaces or another module having that logic and later instantiated
inside the module.
(Please refer to the example below)

interface intf(input bit addsub, input byte data [1:0], output byte q);
function automatic byte add(byte data [1:0]);
return data[0]+data[1];
endfunction
task automatic sub;
q = data[1] - data[0];
endtask
always @*
if (addsub)
q = add(data);
else
sub;
endinterface

module hierRef2(input byte data [1:0], output byte q[1:0]);
intf i1(1'b1, data, q[0]);
endmodule

Regards
Surya








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