Re: [sv-bc] 22.2.2.2 port types

Bresticker, Shalom wrote:
> Hi,
> 
> 22.2.2.2 (ANSI style ports) says,
> 
> "The self-determined type of the port expression becomes the type for
> the port. The port expression shall not be considered an assignment-like
> context. The port expression must resolve to a legal expression for type
> of module port (see 22.3.3). The port expression is optional because
> ports can be defined that do not connect to anything internal to the port."
> 
> I don't understand this paragraph, especially the first and third
> sentences. Can someone explain it to me?
> 
> Thanks,
> Shalom

It is as clear as a Coke bottle ;-)

The first sentence defines the data type presented on the external port.
This is the type that will have to be "assignment compatible" with each
actual instantiation site's corresponding port.

It further establishes that the port expression does not inherit bit width
from its context, or from the instantiation site.
The second sentence means that '{...} cannot be used to pick up the (undefined)
type of the external port, or its correspondent in the instantiation.
The third sentence is a mess.  It needs to refer us to 22.3.3 (which has 8 subsections
of rules about ports).  Maybe I can suggest a better wording for 3 & 4:

"The port expression is optional; when present, it must conform to
 the rules in section 22.3.3 regarding module ports; when absent, the
 external port name is not connected to anything inside to the module."

Although it's not stated, the lack of a port expression
leaves the type of the external port undefined by the first sentence.
The LRM should probably describe whatever is commonly done about this case.
Our synthesis linker accepts anything sent down on that port and no pins are
allocated to it.
The behavior of the corresponding actual port at the instantiation
site seems unimportant for synthesis, but simulator users might
have certain preferences.

Greg Jaxon


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