[sv-bc] 24.3.1 Example without interfaces

Hi,

24.3.1 says,

This example shows a simple bus implemented without interfaces. The
logic type, as used in this example, can replace wire and reg if no
resolution of multiple drivers is needed.

module memMod( input bit req,
bit clk,
bit start,
logic [1:0] mode,
logic [7:0] addr,
inout wire [7:0] data,
output bit gnt,
bit rdy );
logic avail;
..

The statement about the logic type has a couple of problems. This
statement comes from SV 3.0, where logic and reg were different than
what they are today. "reg" was what it was in 1364, a variable and not
just a data type, and could not be used in place of a net, e.g., on the
LHS of a continuous assignment. "logic" was also a variable and not just
a data type, but its semantics were those of a variable of logic type
today. Today a net can also be of type logic.

I would simply delete the sentence.

Thanks,
Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6582
+972 54 721-1033

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