RE: [sv-bc] bit (part) select indexed by variable net connected to output

It seems to me that the rules should be the same as for the left-hand
side of a continuous assignment.
 
However, those rules are not well defined.
 
See Manti 1161, 1565, and 2072.
 
In 1364, the rules for the LHS of a continuous assignment were not
well-defined in the text, but the BNF contained the needed restrictions,
at least most of them, e.g., constant select.
 
However, in 1364, only nets could be the LHS of a continuous assignment.
With the addition of variables on the LHS in SV, the BNF does not
contain the needed restrictions either.
 
Shalom


________________________________

	From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of danielm
	Sent: Monday, April 28, 2008 5:00 PM
	To: sv-bc@server.eda.org
	Subject: FW: [sv-bc] bit (part) select indexed by variable net
connected to output
	
	
	I haven't got any answer so I'm asking once more - are indexed
by variable bit, part select allowed on inout and ouput ports? 

	IMHO this is not covered by LRM.

	module top;
	    int index;
	    wire [3:0] w;
	    reg [3:0] r;

	    sub uut3(r[i]);//???????
	    sub uut4(w[i]);//?????????

	    sub1 uut33(r[i+:2]);//???????
	    sub1 uut44(w[i+:2]);//?????????
	
	endmodule

	
	module sub (output o); //module sub (inout io);endmodule

	module sub1 (output [1:0] o); //module sub (inout [1:0]
io);endmodule

	 

	DANiel

	
	
________________________________

	From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of danielm
	Sent: Friday, April 18, 2008 1:26 PM
	To: sv-bc@server.eda.org
	Subject: [sv-bc] bit (part) select indexed by variable net
connected to output
	
	
	IEEE 1364 disallows to connect to ouput, inout below items:

	Variables
	- Expressions other than the following:
	- A scalar net
	- A vector net
	- A constant bit-select of a vector net
	- A part-select of a vector net
	- A concatenation of the expressions listed above

	SV defines new rules for net and vars - but there is no word
about bit (part) select. Maybe bit/part selects should be also be
mentioned and proper restriction defined (if exists).

	19.12.1 Port connection rules for variables

	- An output port can be connected to a variable (or a
concatenation) of a compatible data type. A continuous assignment shall
be implied when a variable is connected the output port of an instance.
Procedural or continuous assignments to a variable connected to the
output port of an instance shall be illegal.
	- An output port can be connected to a net (or a concatenation)
of a compatible data type. In this case, multiple drivers shall be
permitted on the net as in Verilog.19.12.2 Port connection rules for
nets

	19.12.2 Port connection rules for nets

	- An output can be connected to a net or variable (or a
concatenation of nets or variables) of a compatibledata type.
	- An inout can be connected to a net (or a concatenation of
nets) of a compatible data type or left unconnected, but cannot be
connected to a variable.

	 

	Example:

	module top;
	    parameter p=1;
	    int index;
	    wire [3:0] w;
	    reg [3:0] r;
	

	    sub uut1(r[p]); //allowed
	    sub uut2(w[p]);//allowed
	    sub uut3(r[i]);//???????
	    sub uut4(w[i]);//?????????

	    sub uut1(r[p+:2]); //allowed
	    sub uut2(w[p+:2]);//allowed
	    sub uut3(r[i+:2]);//???????
	    sub uut4(w[i+:2]);//?????????
	
	
	endmodule

	
	module sub (output o); //module sub (inout io);

	endmodule

	 

	DANiel


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