Re: [sv-bc] RE: [sv-ec] svlog enum function usage & maven query

Gordon Vreugdenhil writes:
 > 
 > I personally think that the "Uniform Access Principle"
 > causes far more grief that value; it causes special
 > case rules for various kinds of tfs for backwards
 > compatibility, it means that class static methods
 > are NOT the same as a normal non-class static tf,
 > and it causes additional confusion about the nature
 > of "." as an "operator".
 > 
 > I would be strongly in favor of deprecating the
 > use of unparenthesized calls.

Hear hear!  If you are designing a language from scratch, it
may make sense to follow the UAP.  But in that case, we
wouldn't have $bits(expr), it would be expr.bits instead.
SystemVerilog is so far from uniformly following the UAP
that invoking the UAP for some portions of the syntax just
makes the language less U.

From a purely syntactic point of view VHDL and Ada follow
the Pascal tradition of not having parentheses in subprogram
calls with no arguments.  But even when applied uniformly in
these languages there are special case rules to cover
situations like this:

    function f return record_type is
        variable x, y : integer;
    begin
        y = f.x;
	...

Is this a call to f with field x is selected from the return
type, or is it a scoped reference to local variable x within
function f?

This problem is particularly bad in SystemVerilog because of
the multiple uses of '.' in the syntax.

Paul

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