RE: [sv-bc] merge error on timescale

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Mon Jun 09 2008 - 23:51:11 PDT
So if I have declared a task with delays in $unit, and call it from two
modules following it in the same compilation unit, each having a
`timescale directive, each timescale different from each other and from
the implementation default, what is the timescale used for the task?

Thanks,
Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Rich, Dave
> Sent: Friday, June 06, 2008 1:40 AM
> To: sv-bc@server.eda.org
> Subject: RE: [sv-bc] merge error on timescale
> 
> My view of `timescale is that it is just like any other 
> compiler directive. It is not a statement itself, but effects 
> the processing of certain statements that follow. In this 
> case, it only effects the processing of the definition of the 
> design units that follow it. I see no confusion with 
> statements in $unit.
> 
> Dave
> 
> 
> > -----Original Message-----
> > From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
> On
> > Behalf Of Steven Sharp
> > Sent: Thursday, June 05, 2008 2:56 PM
> > To: sharp@cadence.com; sv-bc@server.eda.org;
> shalom.bresticker@intel.com
> > Subject: RE: [sv-bc] merge error on timescale
> > 
> > 
> > >From: "Bresticker, Shalom" <shalom.bresticker@intel.com>
> > 
> > >So now what about tasks that are declared in %unit?
> > 
> > They have problems similar to those for packages.  They are worse 
> > because a `timescale at the start of the source will not 
> affect them, 
> > so this situation is more likely to arise.  However, I think that 
> > requiring them to have a timescale (if any design elements 
> do) would 
> > also cause a problem.
> > 
> > Add this to the list of disadvantages of the compilation unit as 
> > compared to packages.
> > 
> > Steven Sharp
> > sharp@cadence.com
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Received on Mon Jun 9 23:53:23 2008

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