Re: [sv-bc] Is compiler directive part of `define

From: Greg Jaxon <Greg.Jaxon_at_.....>
Date: Wed Sep 17 2008 - 12:18:07 PDT
Surya,

   The LRM is not clear enough concerning preprocessing to say.
I think it is worth noting that on the dissenting system this
testcase yields an error for any combination of definedness for A and B.
By doing this, it concurs with most human readers who reject this
code as illegible.  The herd accepts the one setting you cited, but
that outcome is just an unfortunate consequence of their common choice
of technology.

  No, your dissenting vendor does not have a bug; other vendors
are not adhering to some obscure corner of the standard which your guy
missed.  They all just use lexical scanners incapable of seeing how
broken this input stream is.  A clearer definition for "ignore" and
for "group of lines" and words about the precedence among the lexical
conventions might explain what the herd is doing, but it would not
acquit them of the charge that they accept this mess.

  The best thing that can be said is that doing it their way keeps
the average cost of EDA low, and filing bug reports with every vendor
in the herd is unlikely to improve the situation.

  The only exception would be a LINT-checking tool that accepts this
without any warning.  I'd file a bug report there. But I'm not sure
what the warning message should say precisely.

Greg Jaxon


Surya Pratik Saha wrote:
> Hi,
> As per LRM, anything after `define is part of that macro until a new
> line is encountered. But I am getting a strange behaviour from a
> particular standard simulator. Consider the following e.g.:
> 
> *`ifdef A `define M module test; endmodule `endif
> `endif
> 
> `ifdef B
> `M
> 
> module top;
> endmodule*
> 
> If I run with +defined+A+B, all the standard simulators consider `endif
> as part of macro 'M' except one, which is actually ending the '`ifdef A'
> with that `endif which is in the same line of macro 'M', and hence
> giving error for the next `endif which is actually ending '`ifdef A'.
> Though that simulator considers `endif as part of another macro which is
> independently declared (not by `ifdef). What should be the ideal
> behaviour. Is that simulator having bug?
> 
> -- 
> Regards
> Surya
> 
> 
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Received on Wed Sep 17 12:18:50 2008

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