RE: [sv-bc] query related with event or operator of Verilog-2001.

Hi,

The 'event or' was deleted from this table because it can not be used in
regular expressions, only in a very particular context.

Please don't send such questions to SV-CC.

Shalom 

> In LRM 1364.2001, section 4.1 contain a table regarding operator.
> The last row of table shows a operator "or"(event or) but 
> this is not present in LRM 1364.2005, section 5.1.
> 
> So should following case be -ve in Verilog-2005.
> 
> module tmp(input in1, in2, output reg out1);
> 
> always@(in1 or in2)
> begin
>     out1 = in1;
> end
> endmodule
> 
> As most of the standard tool don't show error in for above testcase.
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