[sv-bc] simulator behaviour not matching with LRM

Hi,
As per IEEE Std 1364-2005 ,section 5.1.10 (Bitwise Operators ) while 
performing bitwise manipulation of two different sized operands : "When 
the operands are of unequal bit length, the shorter operand is 
zero-filled in the most significant bit positions."
But attached testcase bitwise.v doesnot conform to this while 
simulating  through standard simulator. All of them extending with '1' 
for signed variable.

Again as per IEEE Std 1364-2005 ,section 5.1.13 (Conditional Operator ) 
while performing conditional operation for ambiguous condition and two 
operands with different length : "If the lengths of expression2 and 
expression3 are different, the shorter operand shall be lengthened to 
match the longer and zero-filled from the left (the high-order end)."
But attached testcase conditional.v doesnot conform to this while 
simulating through standard simulator.

Are we missing anything or simulators having bug?

-- 
Regards
Surya




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module conditional;

    reg signed [3:0] a;
    reg signed [7:0] b,c,res_b,res_c;

    reg cond;

    initial
    begin
    
        #5 a = 4'b1011;
           b = 8'b00001011;
           c = 8'b11111011;

           cond = 1'bx;

        #5 res_b = cond ? a : b ;
           res_c = cond ? a : c ;

        #5 $display($time," result = %b, a = %b, b = %b",res_b,a,b);
        #5 $display($time," result = %b, a = %b, c = %b",res_c,a,c);

    end

endmodule
     


module bitwise;

    reg signed [3:0] a;
    reg signed [7:0] b;

    initial 
    begin
    
        #5 a = 4'b1011;
           b = 8'b00001011;
           
        #5 $display($time," a = %b, b = %b, a^b = %b ",a,b,a^b);
    end

endmodule