RE: [sv-bc] simulator behaviour not matching with LRM

These were errors in the LRM, fixed in the draft merged LRM.

The new draft LRM says for the conditional operator, "The first and
second expressions are extended to the same width, as described in
11.6.1 and 11.8.2," where 11.8.2 says,
"When propagation reaches a simple operand as defined in 11.5, then that
operand shall be converted to the propagated type and size. If the
operand shall be extended, then it shall be sign-extended only if the
propagated type is signed." This was fixed in Mantis 1004.

The statement you quoted about the bit-wise operators was simply
deleted, so that 11.8.2 describes what happens. This was fixed in Mantis
1261.

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Surya Pratik Saha
> Sent: Wednesday, November 19, 2008 3:51 PM
> To: sv-bc@server.eda.org
> Cc: Subhasish Saha
> Subject: [sv-bc] simulator behaviour not matching with LRM
> 
> Hi,
> As per IEEE Std 1364-2005 ,section 5.1.10 (Bitwise Operators 
> ) while performing bitwise manipulation of two different 
> sized operands : "When the operands are of unequal bit 
> length, the shorter operand is zero-filled in the most 
> significant bit positions."
> But attached testcase bitwise.v doesnot conform to this while 
> simulating  through standard simulator. All of them extending 
> with '1' 
> for signed variable.
> 
> Again as per IEEE Std 1364-2005 ,section 5.1.13 (Conditional 
> Operator ) while performing conditional operation for 
> ambiguous condition and two operands with different length : 
> "If the lengths of expression2 and
> expression3 are different, the shorter operand shall be 
> lengthened to match the longer and zero-filled from the left 
> (the high-order end)."
> But attached testcase conditional.v doesnot conform to this 
> while simulating through standard simulator.
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