[sv-bc] RE: [sv-ec] RE: [system-verilog] synthesis query for byte/logic initial value

Moving this to the sv-bc, as this is the committee that handles design
issues.

 

 

IMHO, a static variable initialization should be treated as an error
unless the tool is able to connect it to some sort of reset (does anyone
remember Cadence's Synergy?)

 

A const variable should be synthesizable, so I would expect this example
to synthesis to a constant output.

 

 

module test(                     output int result);

  const int factorial_10 = fact(2);

    function automatic int fact;
        input int in;
        if(in == 0)
            fact = 1;
        else
            fact = in * fact(in -1);
    endfunction

    always_comb
    begin
               result = factorial_10;
    end

 

endmodule

 

Dave

 

 

________________________________

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Prakash Barnwal
Sent: Friday, January 23, 2009 4:00 AM
To: Bresticker, Shalom; sv-ec@server.eda.org
Subject: [sv-ec] RE: [system-verilog] synthesis query for byte/logic
initial value

 

Hi Shalom,

 

Thanks alot for this useful information. I need to know your view for
below initialization port initialization case.

In this case , output port result is initialized with factorial_10
(which is 2). Does synthesis tool use this information or put output
port result as floating ?

 

module test(                     output int result);

   int factorial_10 = fact(2);

    function automatic int fact;
        input int in;
        if(in == 0)
            fact = 1;
        else
            fact = in * fact(in -1);
    endfunction

    always
    begin
               result = factorial_10;
    end

 

endmodule

 

Regards,

Prakash

 

 

________________________________

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Friday, January 23, 2009 4:42 PM
To: Prakash Barnwal; sv-ec@server.eda.org
Subject: RE: [system-verilog] synthesis query for byte/logic initial
value

Hi,

 

There is no standard synthesis LRM and this standards committee is not
responsible for synthesis, but I'll answer you anyway.

 

As far as I know, synthesis tool ignore initial assignments to
variables, just like they ignore initial procedures. (Assuming it does
not cause a fatal error.) Unless they appear inside procedural blocks,
in contrast to your examples.

 

So in Testcase 1, the initial value of b would be ignored.

 

In Testcase 2, some tools might allow initial values to const variables
and treat them as similar to parameters, but the initialization of l to
the value of i would have the same problem as b in Testcase 1. Besides,
I don't think the language guarantees that first i is initialized and
then l.

 

Shalom

 

	
________________________________


	From: owner-sv-ec@server.eda.org
[mailto:owner-sv-ec@server.eda.org] On Behalf Of Prakash Barnwal
	Sent: Friday, January 23, 2009 12:15 PM
	To: sv-ec@server.eda.org
	Subject: [sv-ec] [system-verilog] synthesis query for byte/logic
initial value

	Hi,

	 

	I have a query related to byte/logic initial value.

	Could you please reply to below queries?

	 

	Testcase1.

	module test10 (input [3:0] in1, in2,
	             output reg [3:0] out1, out2);

	   byte b = { 1'b1, 1'b0,  1'b1, 1'b0,  1'b1, 1'b0,  1'b1, 1'b0
}; // initialize b

	 

	Ques1. Does system verilog synthesis's LRM allow to consider
initial value of byte b during synthesis ?

	  always@(in1 or in2)
	    begin
	        out1 = b | in2 - in1;
	    end

	   always @(b)// should not fire this block
	    begin
	        out2 = in1 & in2;
	    end

	endmodule

	Testcase2.

	module test (input in1,
	             output reg out1);

	 

	    const int i = 10;    // constant declared with 'const'
	    logic [7:0] l = i;   // initialized with the 'const' value

	Ques2. Does system-verilog synthesis's LRM allow to consider
initial value of logic l (which is 10) during synthesis ?

	    always@(*)
	    begin
	        if (i == l)
	        begin
	            out1 = in1 ;
	        end
	        else
	        begin
	            out1 = 0;
	        end
	    end

	endmodule

	 

	Regards,

	Prakash

	 

	
	-- 
	This message has been scanned for viruses and 
	dangerous content by MailScanner <http://www.mailscanner.info/>
, and is 
	believed to be clean. 

---------------------------------------------------------------------
Intel Israel (74) Limited
 
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

-- 
This message has been scanned for viruses and 
dangerous content by MailScanner <http://www.mailscanner.info/> , and is

believed to be clean. 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.