[sv-bc] RE: [sv-ec] [system-verilog] synthesis query for default value of bit type

Moving this to the sv-bc, as this is the committee that handles design
issues.

 

This is commonly known as the "static initialization order fiasco" in
C/C++. See http://www.parashift.com/c++-faq-lite/ctors.html#faq-10.12.
You cannot depend on the initialization order of static variables; they
are not part of the procedural code. Some day, I would like to see an
order defined within a local scope.

 

As far as considering the initial values of static variable for
synthesis, that should be a tool/user decision. Some simulation tools
have the ability to randomize the initial values, so effectively you
could treat them as unknown.

 

Dave Rich

 

 

 

 

 

________________________________

From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
Behalf Of Prakash Barnwal
Sent: Friday, January 23, 2009 8:06 AM
To: sv-ec@server.eda.org
Subject: [sv-ec] [system-verilog] synthesis query for default value of
bit type

 

Hi,

 

What is default value of bit for synthesis in below example?

module test (input  in1, in2,
             output reg   out2);

   bit  a, b;          

   logic  c = a + b;   // c is immune to change of values of a and b as
it is an initialization.

Ques1. What is the default value of a or b considered during synthesis
in this example?

   always@(in1 <mailto:always@(in1>  or in2)
    begin
        a = in1 ;
        b = in2 ;

       out2 = c;   // c = 0 + 0 [== 0]
    end

endmodule

 

Regards,

Prakash

 


-- 
This message has been scanned for viruses and 
dangerous content by MailScanner <http://www.mailscanner.info/> , and is

believed to be clean. 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.