RE: [sv-bc] delays for strength changes

I verified this for some other simulators.

The situation for $monitor is inconsistent, however, as described in Mantis 1040.

Shalom 


> I tested this in Verilog-XL, to determine the legacy behavior 
> in this case.
> It uses the first delay for a strength change with a value of 
> 1, and the second delay for a strength change with a value of 
> 0, as the LRM text says.
> NC-Verilog has followed this same behavior, and I assume that 
> other simulators have also (either to match Verilog-XL or the 
> LRM text).
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