>From: Gordon Vreugdenhil <gordonv@model.com> >I don't particular like the word "identical" in that sentence >(the old or the new one). That has already caused some >issues in class function prototypes; is "T" identical to >"int" if we have "typedef int T;" ? I was trying to minimize the changes, on the theory that if I don't change the wording, I can't have made it worse. Also to make clear that I am just generalizing the existing Verilog rule to SV, not changing it. However, the word "identical" will probably be interpreted differently for a type than for a range, so a rewording is reasonable. >Is there any reason to not say > > Aside from the signed attribute mentioned below, the data > types between the two declarations of a port shall match. > >That takes away any uncertainty as to whether different >typedefs (or type parameters, etc) can be used to define >the types. It is only the final resolution of the type >that counts. I am OK with that wording. As an alternative, we could require the declarations to have matching syntax, like the declarations of prototype and implementation for extern method declarations. My main goal here is not to have to deal with bizarre expectations of how differing declarations should be combined to get the final type for the port. There is no need to match the random behavior of some other tool, because it is an error. >In addition, I am confused by Brad's example. Certainly >"in" cannot be declared three times. I assume that the >intent was to consider the latter three separate but the first >block as a single example. I assumed as much. >I'd like to make sure as well that we agree as to *why* the >first example block is illegal. "in1" is illegal since the >resulting type of "bit" is not legal for a net; "in1" is >implicitly a net type since "var" is not specified and it >is an input. I disagree with this reason. The declaration bit [5:0] in1; is a variable declaration. It would be treated as a variable declaration if there were no port declaration, and the variable declaration and the port declaration are separate declarations. The reason that this is illegal is that the declaration input [5:0] in1; declares in1 to be a vector of logic, while the variable declaration declares in1 to be a vector of bit. These types do not match. > "in2" is illegal since the type "T" is a >packed [1:5] meaning that the "T [1:10] in2" does not have >the same packed dimensions as "input [1:10] in2" which is >not legal. Yes. > If, however, "T" was just "typedef logic T;", >I would consider that to be legal even though the data >types are not "identical" (the implicit datatype matches >T in this case, but what does "identical" even mean?). I am OK with it either way. I don't think it matters whether we consider this to be legal, since I don't see any reason users would want to declare it this way. We do need to allow some syntactic difference between the two because of the following legacy case: output [5:0] out; reg [5:0] out; Here they have used the default logic type for the port, but explicitly declared the reg type for the variable. If "reg" had been defined to mean "var", then the data types would have had the same syntax on both. But since "reg" was defined to mean "logic", it is part of the data type syntax, so the data type syntax is different between the declarations. This must be allowed. Note that this case is similar to the in1 case, and demonstrates that the second declaration is a variable declaration that causes the port to be treated as a variable. Without the second declaration, this would be a wire. The same was true for in1. >Gord. > >Brad Pierce wrote: >> Following up to http://www.eda-stds.org/sv-bc/hm/8973.html , > > which became Mantis item http://www.eda-stds.org/svdb/view.php?id=2593 , > > which became ballot comment #4, Steven Sharp has uploaded a proposal > > that would clarify that the following declarations are illegal >> >> input [5:0] in1; >> bit [5:0] in1; >> >> typedef logic [1:5] T; >> input [1:10] in2; >> T [1:10] in2; // 1 to 5 varies most rapidly >> >> But the following declarations would still be legal >> >> input var bit [5:0] in; // input variable >> input T [5:0] in; // input net >> input var T [1:10] in; // input variable >> >> -- Brad >> >> >> > >-- >-------------------------------------------------------------------- >Gordon Vreugdenhil 503-685-0808 >Model Technology (Mentor Graphics) gordonv@model.com > > >-- >This message has been scanned for viruses and >dangerous content by MailScanner, and is >believed to be clean. > Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Apr 28 11:07:07 2009
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