RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

Those declarations only differ in kind, not in data type.  Their data types match.

For example, the data types of the following two output ports match

  output var [5:0] out_variable;
  output wire [5:0] out_wire;

and type(out_variable)==type(out_wire) is true.

-- Brad

-----Original Message-----
From: Mark Hartoog [mailto:markh@synopsys.COM]
Sent: Tuesday, April 28, 2009 3:26 PM
To: Brad Pierce; sv-bc@eda.org
Subject: RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

I think it is clear that the following has always been legal verilog:

module test(out);
output [5:0] out;
reg [5:0] out;
endmodule

Doesn't the proposal make that illegal?

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad Pierce
Sent: Monday, April 27, 2009 3:05 PM
To: sv-bc@eda.org
Subject: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

Following up to http://www.eda-stds.org/sv-bc/hm/8973.html , which became Mantis item http://www.eda-stds.org/svdb/view.php?id=2593 , which became ballot comment #4, Steven Sharp has uploaded a proposal that would clarify that the following declarations are illegal

    input [5:0] in1;
    bit [5:0] in1;

    typedef logic [1:5] T;
    input [1:10] in2;
    T [1:10] in2; // 1 to 5 varies most rapidly

But the following declarations would still be legal

    input var bit [5:0] in; // input variable
    input T [5:0] in;       // input net
    input var T [1:10] in;  // input variable

-- Brad



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