>From: Mark Hartoog <Mark.Hartoog@synopsys.com> >I think it is clear that the following has always been legal verilog: > >module test(out); >output [5:0] out; >reg [5:0] out; >endmodule > >Doesn't the proposal make that illegal? I am not sure why you think it would. Brad has addressed the fact that var versus net is not part of the data type, if that was your concern. The data type for the port declaration is "logic [5:0]", where the "logic" is implicit. The data type for the variable declaration is "reg [5:0]". The LRM says that logic and reg denote the same type. So the data types are the same on both. The specification of the data type uses slightly different syntax in the two declarations. The matching required must allow at least this much difference in the syntax. This is where the use of the term "identical" might be considered misleading. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Apr 28 16:33:39 2009
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