RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

Mark,

> If you want identical types, then it is a little unclear if reg and logic are the same.

According to 6.11.2 "logic and reg denote the same type".

> I think you should use some other term.

Agreed. Elsewhere in this thread it has been proposed that "identical" be weakened to matching.

> This proposal seems very weird and unnatural.

Agreed, but so does the LRM section it's trying to repair.

> You are allowed to change the signed attribute between the two declarations
> (because 1364 clearly says you can), but nothing else? That make no sense.
> The signed property is part of the data type. So what you are saying is the
> you can change some parts of the data type and not others.

I agree, highly weird.  But no more weird than "allowed to change the signed attribute between the two declarations".

-- Brad

-----Original Message-----
From: Mark Hartoog [mailto:markh@synopsys.COM]
Sent: Tuesday, April 28, 2009 5:52 PM
To: Steven Sharp; Brad.Pierce@synopsys.COM; sv-bc@eda.org; Mark.Hartoog@synopsys.COM
Subject: RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

It was the term 'identical'. If you want identical types, then it is a little unclear if reg and logic are the same. I think you should use some other term.

This proposal seems very weird and unnatural. You are allowed to change the signed attribute between the two declarations (because 1364 clearly says you can), but nothing else? That make no sense. The signed property is part of the data type. So what you are saying is the you can change some parts of the data type and not others.

The P1800-2005 LRM was very vague about this. At this point a very restrictive interpretation, like is proposed here, will almost certainly cause backwards incompatibility problems for vendors. This means that vendors will probably never implement this or will implement it inconsistently.

-----Original Message-----
From: Steven Sharp [mailto:sharp@cadence.com]
Sent: Tuesday, April 28, 2009 4:25 PM
To: Brad.Pierce@synopsys.COM; sv-bc@eda.org; Mark.Hartoog@synopsys.COM
Subject: RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)


>From: Mark Hartoog <Mark.Hartoog@synopsys.com>

>I think it is clear that the following has always been legal verilog:
>
>module test(out);
>output [5:0] out;
>reg [5:0] out;
>endmodule
>
>Doesn't the proposal make that illegal?

I am not sure why you think it would.

Brad has addressed the fact that var versus net is not part of the data
type, if that was your concern.

The data type for the port declaration is "logic [5:0]", where the
"logic" is implicit.  The data type for the variable declaration is
"reg [5:0]".  The LRM says that logic and reg denote the same type.
So the data types are the same on both.

The specification of the data type uses slightly different syntax in
the two declarations.  The matching required must allow at least this
much difference in the syntax.  This is where the use of the term
"identical" might be considered misleading.

Steven Sharp
sharp@cadence.com


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