RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

>Another option would be to say that if there is both a port declaration and a 
net/variable declaration for the same name, then all type/kind information in 
the port declaration shall be ignored.


That seems pretty close to what Verilog-XL is doing, and I assume lots of
other tools do something like this to be compatible.  I could go along with
this also.

This still leaves the oddity in the LRM text that says you pay attention to
the signed attribute (sic) if it is on the port declaration, even if it is
missing from the net/variable declaration.  Do we need to maintain backward
compatibility with this?

I don't know where this weird signedness rule came from.  It didn't come
from the original implementation in Verilog-XL.  XL actually errors if the
signedness doesn't match, even though it allows range mismatches.


Steven Sharp
sharp@cadence.com


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