RE: Mantis 2593 about non-ANSI port declarations (Was: [sv-bc] Mantis 1111, omitting range on port declaration)

I would strongly oppose this. It would be a super-gotcha! It would be very bad language design and bad programming practice.
To allow specification that has meaning and then ignore it has no justification.
It would mean that one cannot depend on the information in a port declaration.

Shalom



> >Another option would be to say that if there is both a port 
> declaration and a 
> net/variable declaration for the same name, then all 
> type/kind information in 
> the port declaration shall be ignored.
> 
> 
> That seems pretty close to what Verilog-XL is doing, and I 
> assume lots of
> other tools do something like this to be compatible.  I could 
> go along with
> this also.
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