Hi, I have a query related protect directive. In VHDL-2008,there is a directive named "protect directive" which is used for encryption/decryption of the source text. In SV-2009,there is nothing like protect directive of VHDL-2008. So my query is this that whether it is not necessary in Verilog/System verilog or it was overlooked??. Regards, dhiRAj -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Sep 15 06:02:18 2009
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