IEEE Interpretations are the mechanism for working groups to issue formal responses to questions about their published work. Naturally, the range of responses is constrained to not invalidate or alter the published document. A frequent response refers the issue to the working group for consideration in the next version of the standard. Another frequent response connects the dots that may have been missed, thus leading to flawed conclusions about the requirements of the standard. The Verilog/SystemVerilog working group has long managed errata outside of the IEEE Interpretations process, and as such no official guidance has been provided to users of the standard. I don't know whether IEEE policy on errata encourages or discourages this proposed approach, and a question directed up through DASC might be useful to establish where the boundaries are. /sjd jonathan.bromley@doulos.com wrote: >> Is there any objection to us creating a public SV errata/commentary >> wiki, where we could organize these things in a quickly acceesible >> way? Such a page would be unofficial, but might be quite useful. >> > > Some while after the VHDL standard 1076-1987 was first published, > the relevant committee published an "Interpretations" document > for just this kind of reason. I know that it was published as > an IEEE doc, but presumably it did not have the status of a > formal standard. So, at the very least, there is a precedent. > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Oct 2 08:13:16 2009
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