RE: [sv-bc] changing the lifetime of begin end block

OK thx.

As I saw in discussion this is not only single reader problem but also
different tools have different results.
I've add mantis to clear those 2 sentences:
http://www.verilog.org/mantis/view.php?id=2978

DANiel

-----Original Message-----
From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
Sent: Friday, February 12, 2010 7:54 AM
To: Daniel Mlynek; jwill@BasicISP.net; sv-bc@eda.org
Subject: RE: [sv-bc] changing the lifetime of begin end block

We answered this.

6.21 is the subclause that defines this normatively.

23.2.1 just contains an informative high-level description of the module
header. This sentence can be changed since it creates a confusion in at
least one reader.

Shalom

> -----Original Message-----
> From: Daniel Mlynek [mailto:daniel.mlynek@aldec.com.pl]
> Sent: Friday, February 12, 2010 8:01 AM
> To: Bresticker, Shalom; jwill@BasicISP.net; sv-bc@eda.org
> Subject: RE: [sv-bc] changing the lifetime of begin end block
>
> I think that in whole disciussion you've forget about my orginal
> doubt.
> Which is : is automatic lifetime defined for module should change the
> lifetime of the variable defined in begin...end blocks in
> always/initial processes?
> LRM 1800-2009 says: "The module header defines the following: - The
> default lifetime (static or automatic) of subroutines defined within
> the module"
> If this lifetime from module header should change also lifetime of
> variables from begin...end blocks then above sentence should be
> changed. If not then it is ok.
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