Subject: RE: [sv-ec] suggested question for Synopsys and especially Cadence
From: Kevin Cameron (sv-xx@grfx.com)
Date: Sat Dec 07 2002 - 09:31:35 PST
> From: "David W. Smith" <dws@dolcesfogato.com>
>
> Yep.
But the names in a module port list (also enclosed in brackets)
wouldn't be. Maybe I should rephrase the question:
Is it easier/possible to limit the recognition of a "keyword" if
it is in a subscope delimited by (say) brackets?
If there is any benefit to using the second syntax for ease of
retrofitting new functionality into older simulators I'd be happy
to put up with the extra typing.
Kev.
> -----Original Message-----
> From: Kevin Cameron
>
> Another question...
>
> The CC is thinking of using the syntax:
>
> extern <attribute>{,<attribute>} ...
>
> for external functions e.g.:
>
> extern pure,context xfunc();
>
> I presume that would make "pure" and "context" keywords.
> if we change it to:
>
> extern (pure,context) xfunc();
>
> Are they still keywords?
>
> Kev.
>
>
> > From: Stefen Boyd <stefen@boyd.com>
> >
> > David,
> >
> > Since Cadence has begun beating the "no new keywords"
> > drum, I thought it might help all of us (especially
> > users!) to know of any keyword conflicts that can
> > be found by grepping the huge repository of designs
> > that both companies have as part of their test suites.
> > This would give us a real idea of what might happen
> > to legacy verilog if it is used with a SV compliant
> > simulator or synthesis tool that supports the new
> > collection of keywords.
> >
> > Most importantly, it will also greatly help this stuff
> > make it across into 1364 intact.
> >
> > Regards,
> > Stefen
> >
> >
> > --------------------
> > Stefen Boyd Boyd Technology, Inc.
> > stefen@BoydTechInc.com (408)739-BOYD
> > www.BoydTechInc.com (408)739-1402 (fax)
> >
>
>
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