Subject: Re: [sv-ec] Re: $wait_all/any/... (Forward of bounced email from Arturo Salz)
From: Steven Sharp (sharp@cadence.com)
Date: Thu Dec 19 2002 - 15:32:48 PST
>The difference between $wait_all(x,y,z) and @(x && y && z) is that =
>$wait_all actually works whereas the second form doesn't work. Most Verilog
>compilers will = flag that expression as an error, and even if they don't,
>it won't work because = the events will not trigger at the same time.
They better not flag it as an error, since it is legal Verilog. However,
it doesn't mean anything involving events on the three objects. It means
to wait for a change in the value of the expression (x && y && z).
Steven Sharp
sharp@cadence.com
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